Logic Design Engineer II

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Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the Cloud Compute Development Organization (CCDO) is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for an SOC RTL to PD Engineer to join the team.

Required Qualifications:

• MS with 2+ years of experience or BS with 4+ years of experience.
• At least 3+ years of experience applying digital design principles in SOC and/or IP development.
• Strong Static Timing Analysis background; understanding timing signoff fundamentals.
• Experience in EDA tools such as Primetime, StarRC, Design Compiler, ICC, and Innovus.
• Experience with timing constraints management and debug tools supporting constraints quality checks, constraints verification, constraints promotion & demotion.
• Through understanding in writing timing constraints, exceptions, clock constraints; good understanding in SDC commands and TCL constraints.
• Understanding in design closure challenges in power and clock domain crossings.
• Understanding reset and FIFO related design requirements.

Preferred Qualifications

• Experience with FEV and industry standard tools such as Formality and/or Conformal
• Applied understanding of low power design principles.
• Highly Proficient in Verilog/System Verilog coding constructs.
• Knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting)
• Strong understanding in clock crossing techniques
• Strong understanding in IJPF (Low power intent).
• Ability to write scripts using Perl, TCI, Python etc.
• Familiarity with Industry standard interface protocols is a plus.
• Good verbal and written communication skills.

• Ensure high quality deliverables from RTL to Physical Design
• Learn custom synthesis flow and setup and an perform synthesis while ensuring high quality of results
• Create, analyze, and maintain timing constraints/SDCs
• Analyze and drive UPF solutions for low power checks
• Drive RTL to Synthesis FEV clean
• Collaborate with RTL and Physical Design team to address design feedback and drive quality