Silicon Engineer II

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Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate, high-energy engineers to help achieve that mission.

The Data Processing Unit (DPU) team brings together state-of-the-art software and hardware expertise to create a highly programmable and high-performance ASIC with the capability to efficiently handle large data streams. Thanks to its integrated design, this solution empowers teams to operate with increased agility and deliver significantly superior performance compared to CPU-based alternatives

We’re seeking a Physical Design Engineer. As part of our DPU silicon team in Santa Clara, you’ll take on all aspects of Physical Design from RTL to GDS signoff. You’ll tackle key design challenges and work closely with other designers to help drive our chips to tapeout. We’re working on some of the most exciting silicon projects in Microsoft, and you can help us drive our vision.

Required qualifications:

• Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience
  • OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience
  • OR equivalent experience.
• 2+ years of physical design experience, with demonstrated experience in delivering tapeout-ready GDS
• 1+ years experience with Synopsys design tools (e.g., DC, ICC2/Fusion-Compiler, PrimeTime)
• 1+ years experience with physical verification tools (e.g., Calibre) to run DRC/LVS and delivery clean GDS for tapeout

Other qualifications:

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

Preferred qualifications:

• 5+ years of hands-on physical design experience (including synthesis, place & route, LEC, STA, physical verification, and EM/IR closure)
• Experience with flow automation & tool debug
• Understanding of STA & timing constraints
• Demonstrated tapeout experience in TSMC 5nm/3nm or below
• Scripting skills in TCL or Perl

Silicon Engineering IC3 - The typical base pay range for this role across the U.S. is USD $100,600 - $199,000 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $131,400 - $215,400 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:US corporate pay information | Microsoft Careers

Microsoft will accept applications for the role until Aug, 8. 2025

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#SCHIE

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• Take full ownership of important designs and drive them tapeout, meeting all timing, physical, electrical, and manufacturing requirements:
• Perform early design exploration & analysis, giving feedback to RTL team on design issues, and work to resolve them
• Resolve all floorplanning and timing issues; optimize design placement, congestion, clock tree insertion, routing, timing closure
• Perform all signoff activities for tapeout including timing ECOs and signoff timing closure, physical verification, EM/IR, and formal verification
• Work closely with fellow team members to resolve boundary timing issues, make floorplan adjustments, and address timing issues, constraints, etc.